Electrostatic Discharge (ESD):
Where are We Heading ?
EOS/ESD Symposium 2002 General Chairman
ESD Association Board of Director
In the last ESD Journal, in the
article "ESD: Where are We Heading?" the question was
first measured some of the technical vitality in the ESD industry.
Are we as an industry shrinking or growing? Is there a future in
ESD work and products? What does the Semiconductor International
Association (SIA) Technology Roadmap teach us? How does our ESD
roadmap align with the SIA Technology Roadmap? What should our ESD
roadmap look like? Will our ESD technology machine hit the ESD Technology
Wall? Let's keep looking over the dashboard, so we have a sense
where we are going. What is coming down the road? These questions
are being asked by the ESD Association, whose ESD Association Board
of Directors have taken steps to build an ESD Technology Roadmap
Sub-committee to pay attention to our industry.
Part II: Technology and Innovation
ESD has entered the public domain with the first article published
in this year's Scientific American on the ESD industry. The Scientific
American October 2002 article, "Lightning Rods for Nanostructures"
rose interest in the public eye of the kind of issues that the ESD
industry will be grappling with - - how to provide ESD protection
in complementary metal oxide semiconductor (CMOS) technology, silicon
on insulator (SOI), radio frequency (RF) technologies, the magnetic
recording (MR) industry, and masks. How can we see the trends? What
do we measure ?
A quick ESD industry metric to show
the technical vitality is the activity of patents and inventions
in the field of ESD. For those interested, take a quick look at
what we can see from the US Patent Trademark Office (USPTO) Web
site. Go to http://www.uspto.gov, and proceed with a Boolean Search
on ESD. From this, the number of patents per year are grouped in
years. Some interesting trends are evident. Here is what you will
the USPTO database, patents are bucketed into the following groups
based on the date of issue: 1976-1980, 1981-1985, 1986-1990, 1991-1995,
and lastly 1996-2002. The data shown in the plot is the number of
issues in the groupings based on a search of ESD, and the logical
AND-ing of ESD AND CMOS, ESD AND SOI, and lastly ESD AND RF. What
can be seen is that the trend shows a logarithmic increase of issued
patents in each grouping. In 1976 to 1980 there were 24 ESD patents
sited. From 1981 to 1985, 50 were US patents were issued. In 1986-1900
there was a 5X increase to 256, and from 1991 to 1995 the number
issued was 673 and finally, from 1996 to 2002, there were 2991 issued
ESD related patents. Out of the 2991 ESD patents, 1063 were related
to ESD in CMOS technology. In this time frame, the number of RF-ESD
and SOI-ESD related patents were 272 and 195 patents respectively.
Whereas the CMOS ESD patents began at an earlier date, the rate
of growth of patents in other areas are just as rapid, and a key
point is that out of the 2991 ESD issued patents, there is much
activity which is not CMOS technology. Interesting ? Yes, very interesting
In CMOS technology, the nano-structure age has begun where the
silicon MOSFET transistor channel lengths are decreasing below 100
nanometers. MOSFET transistors dimensions are scaled according to
MOSFET constant electric field scaling theory. MOSFET constant electric
field scaling theory scales the dimensions of the transistor to
maintain the same electric field across the oxide film. MOSFET scaling
has reduced the oxide thickness from 1000 A thickness to less than
20 A gate in recent generations. With oxide scaling, the gate dielectric
breakdown voltage decreases. For reasons of dimensional similitude,
the MOSFET channel length and other dimensions decrease. As a result,
the scaling of MOSFETs play a profound role in the ESD robustness
of the MOSFET transistor.
Scaling and the desire for improved
performance has influenced both the silicon devices and wiring interconnect
used in silicon technology. To improve the speed of high performance
semiconductor chips, and to maintain dimensional similitude with
the MOSFET transistor, interconnects are also scaled with the silicon
devices and material changes continue to change. To achieve faster
devices, interconnects have moved from aluminum-based to copper-based
interconnect systems to reduce the resistance. To reduce the line-to-line
and coupling capacitance, new inter-level dielectric (ILD) materials
with lower dielectric constants have continued interest. ESD robustness
of the wire interconnect and ILD dielectric are a strong function
of the material melting temperature, stress characteristics, and
dimensions. The material change, wiring hierarchy and architectures
of the wire interconnects/dielectric system have significant influence
on the ESD robustness of leading edge high-pin count advanced technologies.
Yes, but isn't ESD protection getting
easier in CMOS and due to the learning isn't it getting easier?
Yes, CMOS is maturing and the issues to provide ESD protection to
these technologies are decreasing. But - - the new fields are emerging
rapidly. SOI, RF CMOS.. and other logical extensions.
To maintain performance objectives
in CMOS, it is also possible to develop CMOS technology on insulators
to lower capacitance. This can be achieved by using standard CMOS
technology on a starting silicon-on-insulator (SOI) or silicon on
sapphire (SOS) technologies. Many process technology techniques
exist to form SOI wafers (e.g. SIMOX, SIBOND) and SOS wafers. With
the development of a mainstream SOI technology, SOI technology will
be integrated with both copper interconnects, low k materials and
features used in sub-100 nanometer CMOS technologies. As SOI MOSFET
is scaled, the buried oxide (BOX) layer will also scale to reduce
cost and improve thermal transport to the substrate material. With
the thinning of the silicon film on the BOX layer, both partially
depleted SOI (PD-SOI) and fully depleted SOI (FD-SOI) will become
important. Although it has been demonstrated that good ESD results
are achievable in PD-SOI, continued research and development is
needed in the future for both PD- and FD-SOI devices. As SOI leaves
the niche marketplace, it will be a bigger player with plenty of
interesting work needed in ESD.
Radio Frequency (RF) and GHz Technologies
Focusing on the RF technologies, what do we see? Looking within
the RF ESD group, we can observe that Gallium Arsenide (GaAs) related
ESD patents began at an 1985 time frame due to the long term presence
of the GaAs industry - but much later than the CMOS ESD patents.
RF designers did not concern themselves with ESD issues since RF
GaAs products was a low volume niche market. With the growth in
the wireless market, this has driven more innovation and concerns
about ESD in GaAs. In more recent years between 1996 and 2002, the
growth of ESD patent activities in the Indium Phosphide (InP) and
Silicon Germanium (SiGe) technology has also increased. Silicon
Germanium and Indium Phosphide technologies are recent arrivals
in the technology arena.
the growth of mobility and portability of today's society, radio
frequency (RF) technology and Giga-Hertz (GHz) applications continue
to grow at rapid pace. With the laptop, palm readers, cellular telephones,
and the Internet, the wired and wireless marketplace will have a
rapid growth in the next decade. High speed wired communications
for 10 to 40 GHz Ethernet and SONET will fuel the need for RF technology.
With the increased speed of these wired systems, the loading and
RF quality of ESD protection strategies and components will have
to be re-addressed. These wired systems will contain combinations
of mixed signal chips, RF CMOS, Silicon-Germanium technology, Gallium
Arsenide (GaAs), RF SOI and optical components. ESD will be a threat
and a concern for high speed circuitry in these technologies.
ESD protection will be a concern in RF CMOS for applications
as CMOS moves into the GHz regime. To achieve high unity current
gain cutoff frequencies in transistors, advanced CMOS technologies
will needed to be used. This will require low capacitance and small
MOSFET channel lengths. As a result, ESD devices will be smaller
than standard CMOS technologies. So, the effort and time put into
CMOS technology will be needed as the ESD structures are reduced
in size to achieve RF frequency performance objectives, leading
to more ESD challenges. So just as it looked like CMOS ESD work
was finished, RF CMOS will be highly challenged as it chases applications
being fulfilled by its BiCMOS counterparts. Guess what ? There are
less options for ESD in RF CMOS than RF BiCMOS due to less structures
and levels….So still more challenges to come.
Silicon Germanium (SiGe) technology will be a strong player
in the GHz revolution. SiGe transistors continue to achieve rapid
increases in the transistor speeds pushing unity current gain cutoff
frequencies to 300 GHz. The significant reason which is fueling
the SiGe revolution is that it can be integrated with CMOS technology
in a standard foundry. SiGe applications consist of high speed oscilloscopes,
cellular phones, GPS devices, and high speed wired communication
systems. The understanding of SiGe ESD sensitivity will be of importance
as these products have entered the mobile market. Even today, new
devices such as SiGe:SiGeC hetero-junction bipolar transistors (HBT)
are being explored to further extend the application space and transistor
speeds. ESD issues? Yes, work is ongoing and will need to continue.
ESD publications in SiGe have just begun in the last few years with
more work to go !
Gallium Arsenide (GaAs) has advantageous electrical and thermal
characteristics (e.g. higher Johnson Limit) compared to SiGe devices
allowing dominance in the power amplifier and other markets. GaAs
will be a significant player in optical communication systems. GaAs
lasers will also play a key role in these systems. As in SiGe technology,
GaAs technology will be extended to GaInP and other Gallium compounds
to produce more efficient and faster devices for the future. Today,
the ability to achieve ESD robust GaAs devices has still been a
difficult road. GaAs still has a role and ESD is very important
in places where GaAs chips end up - military, space applications,
satellites, etc…where ESD is important and failure is costly.
What about the magnetic recording industry ?
Magneto-resistive (MR) head devices preceded Giant Magneto-resistive
head (GMR). From the plot, it can be seen that ESD related patents
on MR heads in the recording
began at the recent discovery of the MR head sensitivity to electrostatic
discharge. The first publication on ESD concerns in magnetic recording
heads, written by Wallash, Hughbanks and Voldman, was released at
the 1995 EOS/ESD Symposium. Since that time frame, a flurry of innovation,
patents and publications has continued in the time frame from 1996
to 2002 as evident from the USPTO patent issue growth. In the meantime,
GMR patent innovation has continued to occur with continued growth
in this field.
Magneto-resistive (MR) Heads
Magneto-resistive (MR) read head is used in the hard drive disk
industry for storage of information. The MR head senses a variation
in a magnetic field from the disk as it sweeps over the disk. This
signal is translated into a voltage due to the magneto-resistivity
of the thin film magneto-resistive stripe on the TiC wafer. The
areal density of information on the disk continues to increase forcing
the size of the MR stripe to scale with each disk drive improvement.
The ESD (HBM) sensitivity of a typical MR head is 150 V. These thin
film stripes do not have ESD protection solutions because of the
physical size of the MR head, cost, and they can not be built on
the wafer due to the lack of a silicon wafer. ESD protection of
MR heads is a continued area of research and growth in MR stripe
itself, the armature, head gimbal assembly and other components
of the disk drive system. Areas of research consists of understanding
of magnetic phenomenon, thermal physics, magneto-thermal research,
electrostatics, design characterstics, failure analysis, and failure
mechanisms. A lot of work ahead !
Giant Magneto-resistive (GMR) Heads
Giant magneto-resistors (GMR) heads are devices that follow
the MR head designs to improve signal improvement with the decreased
areal density of the disk. GMR devices utilize a spin valve (SV)
for initialization of the GMR head. GMR heads are scaled in comparison
of MR heads leading to an increased ESD sensitivity (e.g. 30 V)
. GMR heads experience "spin valve reversal" as a result
of the ESD event, causing de-initialization of the magnetic dipole
alignment. This is followed by MR melt damage at higher currents.
Research, design and understanding of the ESD sensitivities of GMR
devices from EOS, ESD and EMI is ongoing today.
What about the future MR devices ?
Tunneling Magneto-resistive (TMR)
Tunneling MR (TMR) head are the next generation which utilizes
multiple control layers allowing the quantum tunneling of current
through a thin film in a transverse fashion. ESD sensitivities of
TMR heads have been shown to be below 10 V HBM protection levels.
Significant research will be needed to evaluate the feasibility
of manufacturing and ESD protection of these elements. Additional
to this device, there are a significant number of alternative MR
heads for the future. It will get harder to manufacture these structures
in the future, leading the need for more manufacturing solutions
in the equipment, garment, packaging and tooling sectors - - from
tweezers to tools.
So, what does this tell us ? It shows that innovation and growth
in this field is continuing at a rapid pace. There is a lot of highway
on the ESD Technology Roadmap to still do business. Many of these
new fields are just beginning!