ON-CHIP ESD PROTECTION FOR INTEGRATED CIRCUITS
An IC Design Perspective

by Albert Z.H. Wang, Illinois Institute of Technology, http://www.iit.edu/-awang

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ESD Journal Rating*:
* The ESD Journal rates books on a system of 4 quill's maximum for the most outstanding.

We find this book to provide an treasure chest of information for the ESD protection design professional. It not only gives the IC designer insight into the methods for on-chip circuits, it allows all circuit engineers to better understand the methods of ESD protection - on or off chip. Professor Wang has made a difficult subject understandable.

This is a must-read for the ESD Design engineer.

303 Pages; The book is divided into the following Chapters:

Chapter1 Introduction
1.1 A Little Historical Story
1.2 ESD Failure-- An IC Reliability Problem
1.3 On-Chip ESD Protection-- General Remedy
1.4 Challenges in ESD Protection Design
1.5 Scope of this Book
References

Chapter 2 ESD Test Models
2.1 Nature of ESD Phemonema
2.2 HBM Model
2.3 MM Model
2.4 CDM Model
2.5 TLP Model
2.6 Other Models
2.7 ESD ZAPPING Tests
2.8 Summary
References

Chapter 3 ESD Protection Circuit Solutions
3.1 On-Chip ESD Protection Mechanisms
3.2 Diode as ESD Protection Elements
3.2.1 Diode Device Physics
3.2.2 Diode in ESD Protection Operation
3.2.3 Diode Parasitic Modeling

3.3 BJT As ESD Protection Element
3.3.1 BJT Device Physics
3.3.2 BJT in ESD Protection Operation
3.3.3 BJT Parasitic Modelling

3.4 MOSFET as ESD Protection Element
3.4.1 MOSFET Device Physics
3.4.2 ggMosfet in ESD Protection Operation
3.4.3 Mosfet Parasitic Modelling

3.5 SCR As ESD Protection Element
3.5.1 SCR Device Physics
3.5.2 SCR ESD Protection Operation
3.5.3 SCR Parasitic Modelling
3.6 Summary

Chapter 4 ESD Protection Circuit Solutions
4.1 Input ESD Protection Schemes
4.1.1 A Primary-Secondary ESD Protection Network
4.1.2 Multiple-Finger ESD Protection Structure
4.1.3 Gate-Coupled MOS ESD Protection Structure
4.1.4 BJT ESD Protection Network
4.1.5 SCR ESD Protection Network

4.2 Output ESD Protection Schemes
4.2.1 Dedicated Output ESD Protection Network
4.2.2 Self-Protection of Output stages

4.3 Power Clamps
4.3.1 NMOS Power Clamp
4.3.2 SCR Power Clamp
4.3.3 Diode String Power Clamp
4.3.4 Switch as Power Clamp
4.4 Summary

Chapter 5 Advanced ESD Protection
Mixed-Signal, RF and Whole-Chip ESD Protection

5.1 ESD Protection for Mixed-signal ICs
5.2 ESD Protection for RF ICs
5.3 Low-Parasitic Multiple-Mode Solutions

5.3.1 A Duel-Direction ESD Protection Structure
5.3.2 An All-in-one Multiple-Mode ESD Protection Design

5.4 Whole-Chip ESD Protection Schemes
5.4.1 Principles for Full-Chip ESD Protection
5.4.2 A Pad + Clamp Scheme

5.5 Non-Portability in ESD Protection
5.6 Summary
References

Chapter 6 ESD Failure analysis and Modeling
6.1 Why ESD Failure Analysis?
6.2 ESD FA Techniques
6.3 Some ESD Failure Signatures
6.4 ESD FA Correlation
6.5 Latent ESD Failure
6.6 ESD Failure Modeling and Cirteria
6.7 Summary
References

Chapter 7 Layout and Technology Influences on ESD Protection Circuit Design
7.1 Layout vs. ESD Protectin
7.2 Regular Layout for ESD Protection
7.3 Special Layout for ESD Protection
7.4 Advanced Layout Design Concepts
7.5 Technology Scaling vs. ESD Protection
7.6 New Technology vs. ESD Protection
7.7 ESD Protection for SOI and SiGe
7.8 ESD Protection for NANO Technology
7.9 Summary
References

Chapter 8 ESD Simulation-Design Methodologies
8.1 ESD Protection Design Methods:
Trials-&-Error versus Predictive
8.2 EDS Design-Simulation: Device Level versus Circuit Level
8.3 ESD Protection Device Modeling
8.4 Mixed-Mode ESD Simulation for Design Prediction
8.5 Mixed-Mode ESD Simulation: Case Study
8.5.1 Understanding ESD Simulation Results
8.5.2 Case 1: NMOS ESD Protection Structures in 0.8um BiCMOS
8.5.3 Case 2. MOS ESD Protection Circuit in 0.35um CMOS
8.5.4 Case 3. Metal Interconnect in ESD Protection Design
8.5.5 Case 4. A Dual-Direction ESD Protection Structure in BiCMOS
8.6 ESD Protection Design Verification
8.7 Summary
References

Chapter 9 ESD- Circuit Interactions
9.1 Chip-Level ESD Protection
9.2 Circuit-To-ESD Influences: Pre-Mature ESD Failures
9.3 ESD-To-Circuit Influences: Circuit Performance Degradation
9.4 Summary
References

Chapter 10 Conclusion Remarks and Future Work
10.1 Conclusion Remarks
10.2 Future Work

Appendix A Summary for ESD Test Standards
References

Appendix B Commercial ESD Testing Systems

Appendix C ESD Protection Circuit Design Checklist

Index

The Author: Albert z. Wang received his PhD in Electrical Engineering from the State University of New York at Buffalo in 1995. After working for the National Semiconductor Corporation in Santa Clara, CA, as a staff R&D Engineer, he joined the Electrical and Computer Engineering Department at Illinois Institute of Technology in 1998. His research interests and publications center on analog, mixed-signal, RF and SoC IC esign, on-chip ESD protection circuit design, IC CAD, and other closely related subjects.

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