Fowler Associates Labs

First Published inEOS/ESD Technology Oct/Nov 1991

The ESD Threat to PCB-Mounted ICs

Charged boards and personnel can create serious ESD problems for
ICs mounted on printed circuit boards.

Warren Boxleitner: Key Tek Instrument Corp., Wilmington, MA 01887

Much effort has been put into characterizing the impact of electrostatic discharge (ESD) on individual integrated circuits (ICs)and on completed equipment such as computers. However, less time has been spent characterizing the ESD threat to ICs mounted on printed circuit boards (PCBs). Since completed equipment can only be manufactured by mounting the ICs on subassemblies, the ESD threat to PCB- mounted ICs is an important concern.

Computer simulations to determine the level of the voltage, power and energy threats to PCB-mounted ICs have shown that the threat level to PCB-mounted ICs may vary by a factor of nearly 100. This variation depends on the ESD source, the discharge point, and the structure and design of the PCB. The computer simulations also show that the ESD threat to ICs mounted on PCBs may significantly exceed the threat to unmounted, individual ICs.

Circuit models were developed to represent ESD occurring directly to and from various portions of typical PCB assemblies. These models were then used in the computer simulations to predict the ESd voltage, power and energy threats to PCB-mounted ICs. Three areas were studied: the source of the threat, the point of discharge on the PCB assembly, and the PCB structure.

The Threat Source

While ESD threats to PCB-mounted ICs may have many sources, three sources are considered most probable:

1. Charge personnel
2. Charged PCB assembles.
3. The combination of a charged person holding a charged PCB (charged PCB-and-person).

Charged Personnel. Often, when people think of ESD sources, they think of ESD from personnel. Unless wrist straps or other static-preventive measures are used, personnel can become charged due to walking or other motion. When charged personnel contact (or nearly touch) metallic portions of a PCB assembly, ESD will occur. The probability of charged personnel causing ESD damage to an IC is especially severe if the discharge from the person is via a metallic object (such as a tool, a ring, a watch band, etc.). This hand/metal ESD results in very high discharge current peaks.

Charged PCB Assemblies. PCB assemblies may be a source of ESD. For example, assemblies can become charged when transported along a conveyor belt, during shipping, or when handled by a charged person. If a charged PCB contacts a conductive surface, or is plugged into a conductive contact with any other source of charge, ESD will occur and discharge the PCB assembly. This is called charged board model (CBM).

Charged PCB-and-Person. If a charged person and a PCB are in conductive contact during the ESD event, the ESD will discharge both the person and the PCB assembly. If a person walks across a carpeted floor while in conductive contact with a PCB assembly, the person and the PCB assembly may become charged. If the PCB assembly then contacts a conductive surface, or is plugged into an equipment assembly, while still in conductive contact with the person, charged PCB-and-person ESD occurs. This is also known as personnel charged board model (PCBM).

The Discharge Point

Discharge points to PCB assemblies can be grouped into three basic categories:

1. ESD directly to IC pins.
2. ESD to PCB traces between ICs.
3. ESD to PCB connector pins.

With the possible exception of connector pins, discharge points could be expected to be physically located almost anywhere on the surface of the PCB assembly.

ESD to IC Pins. The pins of a PCB-mounted IC extend above the surface of the board itself. Because of this, an ESD arc can actually terminate on the pins of an IC. In this case, the ESD current will not travel to the device via a PCB trace. However, any trace connected to the IC pin may alter the character of the ESD threat.

ESD to PCB Traces. Since ICs do not cover the entire surface of a PCB assembly, a PCB trace may be the nearest metallic point to which an ESD threat may occur. In this case, the ESD arc will terminate not on an IC pin, but on a PCB trace between IC pins. This is especially true if the ESD intruder electrode is located very close to a PCB trace, at a point equidistant between two ICs. In this case, the ESD current will flow to the IC via the PCB trace, modifying the ESD current waveform.

ESD to PCB Connector Pins. The connector pins of a PCB assembly are extremely likely to be subjected to ESD when the assembly is being installed in equipment or in a higher-level assembly. Thus, ESD to or from connector pins is often associated with ESD from a charged PCB or a charged PCB-and-person. Like ESD to traces, ESD to connector pins must flow via a PCB trace to the IC.

The PCB Structure

In any ESD event, the character of the ESD threat is determined not only by the source of the ESD, but by the ESD receptor as well. When the receptor is a PCB assembly, the path from the discharge point to the IC, and the path from the IC to the ground reference are important. Also important is the structure of the ground reference. This structure includes the local ground and external ground reference common to both the IC and the ESD source.

Local Ground Structure. The local ground structure of a PCB is the section of the PCB's ground reference that is part of the PCB assembly itself. Multi-layer PCBs with ground plane layers have the most extensive local ground structures. At the other extreme are PCB assemblies where the only local ground reference is provided by a single ground trace to the IC.

External Ground Structure. The local ground of a PCB assembly may be connected to an external ground. This connection may be intentional, (ex: a direct connection to the AC power "green" ground) or unintentional (ex: placing a PCB assembly on a grounded metallic surface). PCB assemblies often have no metallic connection to any external ground (i.e. during transportation). In this case, the only reference to an external ground is via stray capacitance from the PCB assembly to the eternal ground.

Length of PCB Traces. In addition to the PCB ground structure, lengths of the PCB traces are also important. The trace lengths help determine the impedance and resonant frequency of each of the possible ESD current paths to ICs in a PCB assembly.

Comparison Factors

Several factors can influence the ESD threat to ICs mounted on PCB assemblies. Simulations were performed to compare the voltage, power, and energy threats for each of the combinations shown in Fig 1. The voltage, power, and energy threats to an individual device (not mounted on a PCB) were also determined.

The Circuit Models

Three basic sets of circuit models were required to perform the computer simulations:

1. The model for personnel hand/metal ESD.
2. The model for the PCB structure.
3. The model for a device.

These three sets of models were combined in different ways to evaluate the ESD threat levels for the various factors shown in Fig 1.

Personnel Hand/Metal ESD Model. The most complicated model was the model for personnel hand/metal ESD (Fig 2), This model was developed using calculated and measured parameters for personnel inductances, capacitances, and resistances (1,2,3). These values were then adjusted until the predicted ESD current waveform from the model agreed with that of true hand/metal personnel ESD, as measured on 1 GHZ instrumentation (Fig 3) (4).

Figure 2: Simulation model for personnel hand/metal ESD.

PCB Structure Model. For typical PCBs, both calculated and measured parameters for inductances and capacitances (resistances were negligible) were used to develop models. The model included the series inductance () of the PCB trace, the shunt capacitance of the PCB trace (), and the stray capacitance () of the entire PCB assembly (Fig 4). The values of the model parameters are shown in Table 1.

IC Load Model. An IC load impedance may be tens to thousands of ohms. Also, the impedance of an IC is not constant, but varies with the level and duration of the ESD current. 5 This variation differs from IC to IC depending on the IC design and IC manufacturer. A simple resistive IC load of R-500 ohms was used as a reasonable representation of the average device impedance that may be encountered by an ESD pulse.

Conclusions

All the simulations showed that different combinations of PCB structures, discharge points, and ESD sources can result in ESD threat levels which can vary by a factor of nearly 100 for PCB-mounted ICs. Within this variation, however, there was a clear correlation between the source of the ESD threat and the level of the threat. ESD from the combination of a charged PCB-and-person created the most severe threat levels. For a 1 kV charge voltage, the peak power and voltage threats were 2.4 kW and 1.1 kV, while the energy threat was 36 uJ.

The discharge point also correlated with the threat level. The greatest threat occurred for discharges directly to connector or divice pins. The least threat always occurred for discharges to PCB traces between devices.

PCB Structure and Layout. The most important observation for PCB designers was the correlation of PCB structure and ESD threat. ESD conducted to a device through a short trace was worse for PCBs with no ground plane than for multi-layer PCBs using ground and power planes. Finally, the ESD energy threat was consistently worse for PCB assemblies connected to an external ground, rather than for floating PCB assemblies. These results show the structure and layout of a PCB have a significant impact on the ESD threat level experienced by devices mounted on the PCB.

The ESD threat to devices mounted on PCBs can significantly exceed the threat for non-mounted devices. This was especially noticeable for the peak power threat, which could be 100% greater for devices on a PCB than for individual devices. In addition, the voltage threat to PCB mounted devices could be more than 40% greater, and energy threat more than 15% greater than for individual devices.

Design Implications. These results have strong implications for PCB design and for ESD testing for PCB designs. Attempts have been made to correlate the ESD immunity of PCB assemblies to the individual ESD immunities of the devices mounted on the PCB assemblies. Some argue that a PCB assembly should be considered as weak as the weakest IC on the assembly. Others say a PCB assembly should be considered much more immune than the individual ICs, because the PCB is expected to protect the individual ICs.

A meaningful relationship between individual ESD immunity levels of ICs and the ESD immunity level of an entire PCB assembly cannot be established according to the research presented here. For a worst case PCB design, the sensitivity of the entire assembly will be much worse than that of the individual devices. For a best case design, the assembly immunity will be far better than that of the individual devices. As a result, for two different PCB designs including exactly the same devices, the charge voltages associated with a given failure threshold may differ by a factor of four or five. A PCB assembly may be much stronger than its weakest IC link, or it may be much weaker.

As the costs associated with ESD related failures become fore important, the threat of ESD to ICs on PCB assemblies must receive more consideration. Designers of ICs should consider the threat levels for PCB-mounted ICs. Also, designers of PCBs should take advantage of the potential ESD protection offered by the PCB structure itself. PCB designs should not result in ESD immunity levels for assemblies which are inferior to those on individual ICs. Ideally, the immunity of PCB assemblies should be much better than that of the individual ICs.

ESD testing of PCB assemblies is needed to take full advantage of the protection potential afforded by the PCB. If PCB designers are to create designs more immune to ESD, they will need the feedback provided by the ESD testing of PCB assemblies.

Excerpted from a paper presented at the 1990 EOS/ESD Symposium, September 1990, Lake Buena Vista, FL.

References

1. Byrne, W., "Development of Design and Test Procedures to Meet Electrostatic Discharge (ESD)," Midcon/82 Program Record, 1982, pp. 28/4 1-13.
2. Richman, P. "An ESD Circuit Model With an Initial Spike to Duplicate Discharges from Hands with Metal Objects," EMC Technology, Vol. 4 No. 2, Apr-July 1985, pp. 53-59.
3. Richman, P. "The Effects of Hand-Associated Metal Object Geometry and Hand to Object Coupling Impedance on ESD Current Waves," Proc 7th International Zurich EMC Symposium, 1987, pp. 467-472.
4. Institute of Electrical and Electronic Engineers, Guide on Electrostatic Discharge form Personnel and Small Mobile Furnishings: Part I, C62.47, Draft 10, May 23, 1990.
5. Boxleitner, W., "Characterizing the Stress Applied to ICs by Different ESD Tester Circuits," IEEE EMC Symposium Proceedings, Aug 21-23, 1990.