Nikola Tesla Crossword

First Published in EOS/ESD Technology June/July 1991

Qualifying ICs with Charged-
Device-Model Testers

CDM testing is becoming increasingly important, but care
must be taken in selecting the most appropriate test method.

Peter Richman
President
KeyTek Instrument Corp.
Wilmington, MA 01887 USA

Figure 1- Making Waves. The HBM provides energy, while the CDM provides super-fast rise time and high amplitude. HBM and CDM waves shown on the same scales.

The newest ESD test for ICs uses the Charged Device Model, or CDM. It requires that sub-nanosecond risetime, low-energy pulse currents be drawn from on IC pin at a time with all others floating, to represent discharging a charged IC to metal on a handler or bench. The stress applied by the CDM is vastly different from that of the Human Body Model, or HBM (Figure 1).

 

 

 

 

Test Alternatives

CDM testers have just become available, and users have a choice between two approaches to the job:
Doing "Reality." With CDM as with almost any new test standard, there's a point of view that wants to try to duplicate reality. About the only time no one has suggested doing that for a pulsed EMI standard, was for making real lightening to do surge testing!

Simulating Reality. A quite different viewpoint prefers to simulate a reasonably worst-case representation of reality. In other words, the object is to design a repeatable electrical test, that includes the key electrical threat parameters. These include peak voltage and current, risetime, duration, source impedance and so on. See Figure 3.

Figure 3- Simulating CDM reality. The discharge current wave is specified.

Doing "Reality"

For CDM testing, "reality" means first charging an IC to the selected initial test voltage. The IC is then discharged to ground via an arc from a selected pin, using the mechanical motion of an electrode or the IC itself; See Fig. 2.

Figure 2- Attempting to duplicate CDM "reality." The methods is specified. "Field" charging is shown; direct charging may also be used.

 

The process is repeated for every pin on the IC. Mechanical motion is then used either to bring the IC to a socket, or a socket to the IC, to facilitate leakage and/or other tests. These tests are used to determine whether the device still functions properly, and to verify that its characteristics haven't changed.

If the device does pass, the test voltage is raised and the procedure repeated, until the device finally fails. Test voltages range from several hundred to several thousand volts.

Problems

There are three problem areas connected with trying to duplicate reality.

Charging effects. If the charging circuit remains connected during the discharge, it may well affect discharge waveforms. But if it's disconnected, the IC potential may not remain at the correct voltage. In addition, if the impedance of the charging path is too great, leakage and other effects may prevent the IC from ever reaching the desired charge-voltage level. And field-charging the IC, as shown in Figure 2, has other problems as discussed below. In any case, determining how much such effects are distorting test results can be extraordinarily difficult.

Discharging effects. Arc discharges are among the most complex phenomena in physics. Discharge currents can be highly unrepeatable in risetime, wave-shape and amplitude.

Uncertain test outcomes that result from such unrepeatability can quickly discredit a test standard and testers based on it. This is exactly what has happened with the most widely-known standard for ESD testing of completed equipment, IEC 801-2. It has recently been forced to change over to a so-called contact-mode, relay-based test, from its original air-discharge test.

Variables that can materially influence a gas discharge (whether the gas is air or some more "stable" medium such as nitrogen) include electrode shapes, electrode material and surface contamination the approach speed of one electrode towards the other, and humidity.

Measuring between test sequences at ascending voltage levels. Still another problem is that doing leakage or any other kind of testing on the IC during and after the test sequence, involves transporting it manually or robotically into a test socket. This can introduce the reliability problems of the robot. It also requires great care to avoid introducing extraneous charges and discharges of the IC, during the repeated transfers required between the test and measuring locations.

Making this situation still worse is the fact that after some devices fail due to a CDM zap, they may recover following a subsequent zap.

For such devices, it may therefore be necessary to measure device parameters more frequently, i.e. even between zaps or small groups of zaps. This can result in much additional manual or robotic handling, with its potential associated problems.

Dealing With Them

Ways of trying to deal with problems arising from doing "reality" can significantly increase the cost and complexity of the CDM test, and even its credibility.

One method is to use dry nitrogen as the environment in which the gas discharge takes place. A second is to charge the IC via an external field, instead of connecting it to a known voltage. This charging method, the one actually shown in Figure 2, makes the IC's actual voltage extremely difficult to confirm by measurement.

Finally, a way of dealing with the electrode problem involves careful selection of the tester electrode's material, shape, and finish. However, literally nothing can be done about the material, shape or finish of the IC pin to which the gas discharge takes place. Among other things, the IC pin can be extremely sharp, which can lead to corona effects and consequent test uncertainties, no matter what design skills are brought to bear on the tester's own discharge electrode.

Simulating Reality

For CDM as with any other kind of testing, reality can be simulated only after it's been measured. And the way to measure it-- current waves and so on-- is using a laboratory-type, "real" CDM test setup. Well, if that can be done, why not use that setup as a reality-based tester? There are compelling reasons.

One is that to do the measurements on which to base a standard, the test setup has to work just for a short period, not for months or years in the engineering or QC lab.

Another is that for lab results, you can introduce idealized conditions for some of the parameters which you can't control in real testing. Prime examples are the shape, material, and finish of the IC pin. For your lab test, you can use a rounded ball with no sharp points, made of an optimum metal with a perfect finish; or you can dispense with the pin altogether and just measure a simple calibration block, that is shaped to look like a (fictitious), leadless IC.

Examples of successful simulation that are close to home are the MIL-STD-883C and EOS/ESD Association HBM test standards. Instead of trying to reproduce airdischarge "reality," these standards use relay simulation. It's based on the repeatable arc between a relay's contacts, just before they actually close.

Another key aspect of the HBM simulation is use of a standard representation of the HBM ESD wave which isn't, if fact, real-- but it does the job. And a major advantage o this HBM simulation-- and the CDM simulation of Figure 3-- is that devices can remain socketed during the test, so that no manual or robotic handling is required in order to make parametric measurements as frequently as may be required.

Making the Choice

Clearly the writer is in favor of simulating reality instead of trying to duplicate it. It's not that duplicating it must always fail, it's just that it usually does.

As already mentioned, the IEC 801-2 standard for ESD testing of completed equipment (not ICs) is a case in point. Its original 1984 issue tried to duplicate reality, but it yeilded unrepeatable test results. The outcome is a wholly new revision of the IEC 801-2, which is about to be published.

Not coincidentally, in connection with the CDM test issue, this new revision repudiates air-discharge ESD testing in favor of relay-based, so-called contact-mode testing. Thus it now calls for simulating a reasonable worst-case reality, instead of trying to duplicate it. That lesson shouldn't be lost in connection with CDM ESD testing for integrated circuits.

Conclusions

HBM testing of ICs for ESD susceptibility is fully accepted. Now CDM testing is becoming more an more important as a complementary requirement. As it does, the choice must be made between two different approaches.

One approach attempts to duplicate reality. Another approach provides an electronic representation of an agreed-upon reality, on a basis that can be repeated for millions or even billions of tests, independent of environment and many other variables that may be difficult to control.

These two basic test alternatives usually exist in new technologies. While the outcome for CDM can't be predicted, prior experience suggests that repeatable simulation tests will usually supersede tests that attempt to imitate nature, with all of its complexity and uncertainty.